1. Field of the Invention
The present invention relates to a clock supply circuit, and more particularly to a clock supply circuit operating to control an inner clock skew.
2. Description of the Prior Art
In a clock supply circuit in large-scale integrated circuit, the number of flip-flops (F/Fs) which are connected to clock lines is extremely large, and the length of the lines between these flip-flops is long. Therfore, the design of the clock system becomes difficult, and various other problems occur. For example, a delay between two of the flip-flops or an inner clock skew and a time delay while a clock signal supplied from outside of the chip is inputted into the flip-flops in the chip or an outer clock skew are increased. When the outer clock skew is increased, the performance of the LSI is lowered. Accordingly, it is desired to make the outer clock skew as small as possible.
If when the inner clock skew (hereinafter only called clock skew) is increased, a data transfer error occurs between flip-flops which are connected in series, the error causes erroneous operation of the LSI circuit.
For example, in the case when two flip-flops are connected in series, if the degree of a signal transmission delay between a Q output of a flip-flop in a front stage and a D input of flip-flops in a rear stage is smaller than the clock skew, the flip-flops in the rear stage inputs the Q output in the same clock cycle, so that erroneous operation occurs.
To avoid the occurrence of this phenomenon, the delay between the Q output and the D input of the two flip-flops is controlled to be larger than the clock skew. However, when this value is increased, the operation speed of the LSI becomes slower. Accordingly, it is necessary to control the clock skew to be as small as possible.
FIG. 1 shows an example of a centralized system which is also a clock drive system for a group of flip-flops according to the prior art. In this drawing, F/F indicates a flip-flop and BU indicater clock buffer or buffer. Each flip-flop is so connected to a buffer (BU) 1 and a buffer (BU) 2 in a branch structure. The outer clock is inputted into the buffer 1 first, is then inputted into the buffer 2, and thereafter transmitted into each flip-flop from the buffer 2. By arranging the inner clock lines into such a branch form, the difference of the line distance between the buffer 2 to each of the flip-flops is made small, so that the delay between the lines can be controlled to be relatively small. Accordingly, the clock skew can be also controlled to be small.
However, when the circuit scale of the LSI circuit becomes extremely large as in recent practice, the number of flip-flops in some chips reaches several thousands, the total length of the clock lines becomes collectively large, and the difference in the line length from the output of the buffer 2 to each the flip-flops also becomes large.
FIG. 2 shows an example of a distributed drive system which is another clock drive system according to the prior art.
In this drawing, as is similar to FIG. 1, F/F indicates a flip-flop and BU.sub.1a, BU.sub.2a, . . . , BU.sub.Na-1, and BU.sub.Na (N is a natural number of 1 or more) indicate buffers. Each flip-flop is connected in series to each of the buffers BU.sub.2a, BU.sub.3a, . . . , and BU.sub.N3. In this example, the buffers are are arranged and operated in two phases. The buffer 1a generated in a first phase drives the buffers 2a, . . . , and Na (N is a natural number of 2 or more) operated in a second phase, and also drives each of the flip-flops which are dependent on each buffer.
In this drive system, for example, the drive ability .beta..sub.2 and the drive ability .beta..sub.Na- 1 of the buffer 2a and the buffer Na-1 which respectively have different numbers of the flip-flops are determined in the following manner.
Namely, a delay time t.sub.2A2B between a point 2A and a point 2B, and a delay time T.sub.2A2C between a point 2A and a point 2C are determined, and then load C.sub.2D2E between a point 2D and a point 2E in one clock line, and load C.sub.2F2G between a point 2F and a point 2G in the other clock line are determined; Then .beta..sub.2 and .beta..sub.Na-1 are so determined as to satisfy the following equation: EQU t.sub.2A2B +T (.beta..sub.2, C.sub.2D2E)=t.sub.2A2C +T (.beta..sub.Na-1, C.sub.2F2G)=Constant,
(where T is delay time for driving each load).
In the centralized drive system shown in FIG. 1, for example, the line length from a point 1A to a point 1B is different from that from point 1A to a point 1D. Accordingly, a clock delay caused by RC delay on the line occurs, and a clock skew corresponding thereto also occurs. Namely, the clock skew cannot be avoided by the drive system in principle. Particularly, when the scale of the LSI circuit is large, the magnitude of the clock skew cannot be ignored. Moreover, since the system is a collective drive system, it is necessary for the buffer 2 to have a large drive ability to operate the plurality of the flip-flops. Accordingly, a large amount of current should flow locally in the buffer, thus noise and erroneous operation are likely to occur.
While, in the distributed drive system in FIG. 2, complex calculation is required in order to minimize the clock skew, it is also required to provide a plurality of buffers respectively having different drive abilities, thus the circuit design of the system becomes very complex.
When the number of the flip-flops which connected to a specific buffer becomes large, a clock skew occurs between both the terminals of these flip-flops which cannot be ignored.